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INTEGRATED CIRCUITS
DATA SHEET
SAA7366 Bitstream conversion ADC for digital audio systems
Preliminary specification File under Integrated Circuits, IC01 May 1994
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for digital audio systems
FEATURES * Integrated buffers for simple interfacing to analog inputs * 4 flexible serial interface modes * Overload detection of digital signal -1 dB amplitude * Selectable high-pass filter * 18-bit serial output * 3.4 to 5.5 V operation of digital part * Standby mode * SO24 package * Small non-critical PCB layout. GENERAL DESCRIPTION The SAA7366 is a CMOS cost effective stereo analog-to-digital converter (ADC) using the Philips bitstream conversion technique. QUICK REFERENCE DATA SYMBOL VDDD VDDA fi THD + N DR PARAMETER digital supply voltage analog supply voltage clock input frequency total harmonic distortion + noise dynamic range 3.4 4.5 4.608 - 90 MIN. 5.0 5.0 12.288 - - TYP. 5.5 5.5 13.568 -80 - MAX. APPLICATIONS
SAA7366
The device is designed for digital acquisition of analog audio signals for digital audio systems such as: * CD-recordable * Digital Compact Cassette (DCC) * Digital Audio Tape (DAT).
UNIT V V MHz dB dB
ORDERING INFORMATION PACKAGE TYPE NUMBER PINS SAA7366T(1) Note 1. Plastic small outline package; 24 leads; body width 7.5 mm; (SOT137A); SOT137-1; 1996 Oct 29. 24 PIN POSITION SO24L MATERIAL plastic CODE SOT137A
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Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for digital audio systems
BLOCK DIAGRAM
SAA7366
VSSA 13 operational amplifier 10 k BIR BOR 16 17 3 k 1 pF 10 k 3 k operational amplifier
VREFR 15
TEST2 12
TEST1 10
STD 2
REFERENCE VOLTAGE GENERATOR
CLOCK GENERATION AND CONTROL
4
CKIN
6 VDACN 18 SIGMADELTA MODULATOR 14 REFERENCE CURRENT GENERATOR SIGMADELTA MODULATOR TIMING GENERATOR DECIMATION FILTER STAGE 2 STAGE 1 COMB 3 HALF-BAND FILTERS FILTER 3 5
VSSD V DDD OVLD
I REF
VDACP
19
SAA7366
20 21 3 k 1 pF 3 k 10 k REFERENCE VOLTAGE GENERATOR HIGH-PASS FILTER
BOL BIL
10 k operational amplifier 23
7 SERIAL OUTPUT INTERFACE 8 9
SDO SWS SCK
operational amplifier 22 VREFL 11 HPEN 24 SLAVE 1 SFOR
VDDA
MGA911
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for digital audio systems
PINNING SYMBOL SFOR STD OVLD CKIN VDDD VSSD SDO SWS PIN 1 2 3 4 5 6 7 8 DESCRIPTION
SAA7366
Serial interface output format select. Output format is selected as follows: SFOR HIGH = Format 1; SFOR LOW = Format 2. Standby mode input (active LOW). Overload indication output. This pin indicates whether the internal digital signal is within 1 dB of maximum. In standby mode this output is high impedance. System clock input. Supply for the digital section (3.4 to 5.5 V). Ground supply for the digital section. Serial interface data output. In standby mode this output is high impedance. Serial interface word select signal. In master mode this pin outputs the serial interface word select signal. In slave mode this pin is the word select input to the serial interface. In standby mode this pin is always an input (high impedance). Serial interface clock. In master mode this pin outputs the serial interface bit clock. In slave mode this pin is the input for the external bit clock. In standby mode this output is high impedance. Test input 1. This pin should be left open-circuit. High-pass filter enable input. (HPEN HIGH = enabled). If unconnected this pin defaults HIGH. Test input 2. This pin should be left open-circuit. Ground supply for the analog section. Current reference output node.
1 2VDDA
SCK
9
TEST1 HPEN TEST2 VSSA IREF VREFR BIR BOR VDACN VDACP BOL BIL VREFL VDDA SLAVE
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
reference generator output for the right channel analog section.
Buffer operational amplifier inverting input for right channel. Buffer operational amplifier output for right channel. Negative 1-bit DAC reference voltage input, connected to 0 V. Positive 1-bit DAC reference voltage input, connected to +5 V. Buffer operational amplifier output for left channel. Buffer operational amplifier inverting input for left channel.
1 2VDDA
reference generator output for the left channel analog section.
Supply for the analog section. Serial interface operating output mode master/slave select as follows: HIGH = slave mode; LOW = master mode. If unconnected the pin will default LOW.
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Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for digital audio systems
SAA7366
respectively. By the choice of feedback component values, the application signal amplitude can be matched to the requirements of the ADC. Typically the operational amplifiers are configured as low-pass filters with a gain of 1 and a pole at approximately 5fs. Remark: The complete ADC is non-inverting. Hence a positive DC input (referenced to Vref) will yield a positive digital output. Input level The overall system gain is proportional VDDA, or more accurately {V(VDACP) - V(VDACN)}. For convenience the ADC input signal amplitude is defined as that amplitude seen on BOL or BOR, the operational amplifier outputs (i.e. the input to the Sigma-Delta modulator). Also, the 0 dB input level is defined as that which provides a -1 dB (actually -1.08 dB) digital output, relative to full-scale swing. This offset provides headroom to accommodate small random DC offsets without causing the digital output to clip. Hence: V ( V DACP ) - V ( V DACN ) V I ( 0 dB ) = --------------------------------------------------------------- = V (RMS) 5 The user of the IC should ensure, that when all sources of signal amplitude variation are taken into account, the maximum input signal should conform to the 0 dB level. If not, clipping may occur. In the event that the maximum signal level cannot be pre-determined, e.g. a live microphone input, the average signal level should be set at -10 to -20 dB down. The exact value will depend on the application and the balance between head room and operating signal-to-noise ratio. Behaviour during overload As defined earlier the maximum input level for normal operation is 0 dB. If the input level exceeds this value clipping may occur. Infringements are limited to the maximum permitted positive or negative values, 217 - 1 or -217 respectively. If the high-pass filter has been enabled the clipped output samples may have non-maximum values due to the removal of the DC content. Input signals in the range of 0 to 1 dB may or may not be clipped depending on the values of DC dither and small random offsets in the analog circuitry. When using the recommended application circuitry, clipping will initially be observed on negative peaks due to the use of negative DC dither. The maximum level of overload that can be safely tolerated is application circuit dependent. In the case of the
SFOR STD OVLD CKIN V DDD VSSD SDO SWS SCK
1 2 3 4 5 6 SAA7366 7 8 9
24 23 22 21 20 19 18 17 16 15 14 13
MGA912
SLAVE VDDA VREFL BIL BOL V DACP VDACN BOR BIR VREFR I REF VSSA
TEST1 10 HPEN 11 TEST2 12
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION General The SAA7366 is a bitstream conversion CMOS ADC for digital audio systems. The conversion is achieved using a third order Sigma-Delta modulator (SDM), operating at 128 times the output sample frequency (fs). The high oversampling ratio greatly simplifies the design of the analog input anti-alias filter. In most cases the internal buffer operational amplifier, configured as a low-pass filter will suffice. The 1-bit code from the Sigma-Delta modulator is filtered and down-sampled (decimated) to 1fs in two stages of filtering. An optional high-pass filter is provided to remove DC, if required. The device has been designed with ease of use, low board area and low application costs in mind. Clock frequency The external clock, input on pin CKIN, operates at 256 times fs, which can range from 18 kHz to 53 kHz. Input buffer Two input buffers are provided, one for each channel, for signal amplitude matching, signal buffering and anti-alias filter purposes. These are configured for inverting use. Access is provided by pins BIL, BIR (inverting inputs) and BOL, BOR (outputs) for left and right channels May 1994 5
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for digital audio systems
recommended circuit the following applies: the inverting operational amplifier inputs BIL/BIR are protected from excessive voltages (currents) by diodes to VDDA and VSSA. These have absolute maximum ratings of IIK = 20 mA, with a safe practical limit of 2 mA. Given the input resistor of 10 k, 2 mA diode current and the operation of the operational amplifier a maximum signal (applied to the input resistor) of 30 V can be handled safely. This level represents an overload of 26 dB. During overload the in-band portion of the waveform will be correctly converted. The out-of-band portion will be limited as detailed above. Sigma-Delta modulator The SAA7366 has two third order Sigma-Delta modulators with a quantization noise floor of approximately -104 dB. The scaling of the feedback has been optimized for stable operation even during overload. Thus with a maximum signal swing of 0 V to VDDA on the input the digital output remains well behaved, i.e. it does not burst into random oscillation. During overload the output is simply a clipped version of the input. The gain of this stage is -4.95 dB. Decimation filter Decimation from 128fs is performed in two stages. The first stage is a comb filter, which decimates from 128 to 8fs. The second stage, consists of 3 half-band filters, each decimating by a factor of 2. The overall characteristics are given in Table 1. Table 1 Overall filter characteristics. ITEM CONDITION VALUE (dB) 0.1 -0.5 -60 110 3.87 Table 2 High-pass filter characteristics. ITEM Pass band ripple Pass band gain Droop Attenuation at DC Dynamic range Serial interface at 0.00045fs at 0.00000036fs 0 to 0.45fs
SAA7366
CONDITION
VALUE (dB) none 0 0.029 >40 116
The serial interface provides 2 formats in both master and slave modes (see Figs 3 and 4). In both modes the interface provides up to 18 significant bits of output data per channel. During standby mode (STD = LOW) all interface pins are in their high-impedance state. On recovery from standby the serial data output SDO is held LOW until valid data is available from the decimation filter. This time depends on whether the high-pass filter is selected or not as follows: HPEN = 0; T = 1024/fs, T = 21.3 ms when fs = 48 kHz HPEN = 1; T = 8192/fs, T = 170.6 ms when fs = 48 kHz Overload Detection Indication (OVLD) The OVLD output is used to indicate whenever the data, in either the left or right channel, is within 1 dB of the maximum possible digital swing. When this condition is detected the OVLD output is forced HIGH for at least 512fs cycles (10.6 ms at fs = 48 kHz). This time-out is reset for each infringement. Standby mode (STD) The STD pin activates a power saving mode when the device function is not required. This pin can also be used as a chip enable, as follows. On a HIGH-to-LOW transition, of the STD pin, the internal control circuitry starts a timed power-down sequence. This takes approximately 32 system clock cycles to complete. Transitions on STD which are shorter than 32 clock cycles have an indeterminate effect. However, the device will always recover correctly.
Pass band ripple 0 to 0.45fs Hz 0.45 to 0.47fs Stop band Dynamic range Gain High-pass filter >0.55fs 0 to 0.42fs DC
An optional high-pass filter is provided to remove unwanted DC components. The operation is selected when HPEN is HIGH. The filter has the characteristics given in Table 2.
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Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for digital audio systems
During standby the following occurs: * The internal logic clock is disabled * The serial interface pins are forced to high impedance * The OVLD output is forced LOW * The analog circuitry is disabled * The nominal external analog node voltages are maintained by a low-power circuit. This feature ensures a fast recovery from standby mode.
SAA7366
On a LOW-to-HIGH transition the device reverts back to its normal function. This process takes approximately 32 system clock cycles. Before SDO is enabled the output data is forced LOW. SDO remains LOW until good data is available from the decimation filter. The STD pin has a Schmitt-trigger input. A simple power-on reset function can be effected using an external capacitor to VSSD and resistor to VDDD.
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDA VI IIK VO IO IDDtot ISStot Tamb Tstg Ves1 Ves2 Notes 1. VSSD and VSSA pins must be externally connected to a common potential. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor with a rise time of 15 ns. 3. Equivalent to discharging a 200 pF capacitor via a 2.5 H series inductor. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. CHARACTERISTICS VDDD = 3.4 to 5.5 V; VDDA = 4.5 to 5.5 V; Tamb = -40 to +85 C; fs = 18 to 53 kHz; unless otherwise specified. SYMBOL Supply VDDA IDDA VDDD IDDD Ptot May 1994 analog supply voltage analog supply current digital supply voltage digital supply current total power consumption fs = 48 kHz fs = 48 kHz 7 fs = 48 kHz 4.5 - 3.4 - - 5.0 13 5.0 56 345 5.5 - 5.5 - - V mA V mA mW PARAMETER CONDITIONS MIN. TYP. MAX. UNIT PARAMETER analog supply voltage DC input voltage DC input diode current DC output voltage DC output source or sink current total DC supply current total DC supply current operating ambient temperature storage temperature electrostatic handling electrostatic handling note 2 note 3 CONDITIONS note 1 MIN. -0.5 -0.5 - -0.5 - - - -40 -65 -2000 -200 MAX. +6.5 +6.5 20 VDD + 0.5 20 0.5 0.5 +85 +150 +2000 +200 V V mA V mA A A C C V V UNIT
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for digital audio systems
SYMBOL ISTD PSTD PARAMETER standby supply current standby power consumption CONDITIONS - - MIN. 65 325 TYP. - -
SAA7366
MAX.
UNIT A W
Digital part: inputs SFOR, SLAVE AND HPEN VIL VIH ILI CI CLKIN VIL VIH ILI CI VIL VIH VI ILI CI LOW level input voltage HIGH level input voltage input leakage current input capacitance note 2 -0.5 0.7VDDD -10 - note 1 note 1 note 2 -0.5 2.4 - -10 - - - - - - - 600 - - +0.3VDDD VDDD + 0.5 +10 10 V V A pF LOW level input voltage HIGH level input voltage input leakage current input capacitance note 1 note 1 note 2 -0.5 2.0 -10 - - - - - +0.8 VDDD + 0.5 +10 10 V V A pF
STD (SCHMITT-TRIGGER) LOW level input voltage HIGH level input voltage input hysteresis input leakage current input capacitance +0.4VDDD VDDD + 0.5 - +10 10 V V mV A pF
Digital part: Input/Outputs SWS AND SCK VIL VIH ILI CI VOL VOH CL LOW level input voltage HIGH level input voltage leakage current in 3-state input capacitance LOW level output voltage HIGH level output voltage output load capacitance IO = -400 A; note 1 IO = 20 A; note 1 note 1 note 1 note 2 -0.5 2.0 -10 - - 2.4 - - - - - - - - +0.8 VDDD + 0.5 +10 10 0.4 - 50 V V A pF V V pF
Digital part: Outputs OVLD VOL VOH CL LOW level output voltage HIGH level output voltage output load capacitance IO = -400 A; note 1 IO = 20 A; note 1 - 2.4 - - - - 0.4 - 50 V V pF
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Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for digital audio systems
SYMBOL SDO VOL VOH ILI CL LOW level output voltage HIGH level output voltage leakage current in 3-state output load capacitance IO = -400 A; note 1 IO = 20 A; note 1 note 2 - 2.4 -10 - - - - - 0.4 - +10 50 PARAMETER CONDITIONS MIN. TYP.
SAA7366
MAX.
UNIT
V V A pF
Digital part: timing CKIN tr tf fi msr clock input rise time clock input fall time clock input frequency mark-to-space ratio note 3 fs > 32 kHz fs 32 kHz Serial interface master and slave modes (see Figs 5, 6 and 7) SCK tr tf tL tH fclk tidle SWS tr tf twL twH fwc td td tsu SDO th tsu tr tf data output hold time data output set-up time data output rise time data output fall time note 4 note 4 100 100 - - - - - - - - 50 50 ns ns ns ns word select rise time word select fall time word select LOW time word select HIGH time word select frequency word select delay from SCK word select delay from SCK master mode slave mode note 4 note 4 T = 1/fs T = 1/fs - - 0.45T 0.45T 1fs -50 50 150 - - 0.50T 0.50T 1fs - - - 50 50 0.55T 0.55T 1fs +50 - - ns ns ns ns ns clock rise time clock fall time clock LOW time clock HIGH time clock frequency burst clock idle time note 4 note 4 T = 1/64fs T = 1/64fs master mode slave mode slave mode; T = 1/fs - - 0.40T 0.40T 64fs - 0 - - - - 64fs - - 50 50 0.60T 0.60T 64fs 64fs 0.05T ns ns - - 4.608 40 30 - - 12.288 - - 10 10 13.568 60 70 ns ns MHz % %
word select set-up time to SCK slave mode
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Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for digital audio systems
SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA7366
MAX.
UNIT
Analog part (VDDD = VDDA = 5 V; Tamb = 25 C; fs = 48 kHz) VOLTAGE REFERENCE: VREFL AND VREFR VO Zn Zs VO IO VI VDACP VI Voffset RLmax ZO THD + N input voltage - - decoupled to VREF f = 0 to 20 kHz - - - VDDA < 10 10 100 -85 - - - - - V BUFFER OPERATIONAL AMPLIFIERS: BIL, BOL, BIR AND BOR input offset voltage maximum load resistance; (drive capability) output impedance total harmonic distortion plus noise mV k dB output voltage DC impedance DC impedance normal mode standby mode 0.475VDDA - - - R = 33 k - - 0.5VDDA 750 100 0.525VDDA - - - - - V k
CURRENT REFERENCE: IREF output voltage output current 0.5VDDA 76 V A V
DAC REFERENCE: VDACN input voltage VSSA
ADC PERFORMANCE; NOTE 5 tgd sb DR THD + N S/N cs G Notes 1. Minimum VIL, VOL and maximum VIH, VOH are peak values to allow for transients. 2. ILImin and ILOmin measured at VI = 0 V; ILImax and ILOmax measured at VI = VDDD. 3. fi is a multiple (x256) of the system sampling frequency (fs) which can vary between 18 kHz and 53 kHz. 4. CL = 50 pF (valid for master mode only). 5. Device measured with external components shown in recommended application diagram Fig.8. 6. Input is 1 kHz and -60 dB. 7. Input is 1 kHz and 0 dB. 8. Measured by applying a 1 kHz, 0 dB signal to one channel and monitoring the level of 1 kHz (fundamental) on the other channel. 9. See also Section "Input level" of Chapter "Functional description"; valid for left or right channel. group delay stop band attenuation dynamic range total harmonic distortion plus noise signal-to-noise ratio channel separation gain T = 1/fs f > 0.546fs note 6 note 7 A-weighted note 8 note 9 tbf 60 90 - - - -1.2 - - - - tbf tbf -1 tbf - - -80 - - -0.8 s dB dB dB dB dB dB
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1 STEREO WORD FORMAT 2 SWS FORMAT 1 LEFT DATA 18 CLOCKS SCK 14 CLOCKS 18 CLOCKS RIGHT DATA 14 CLOCKS LEFT DATA RIGHT DATA
Philips Semiconductors
Bitstream conversion ADC for digital audio systems
11
SDO
MSB
LSB
MSB
LSB
MSB
MGA914
Preliminary specification
SAA7366
Fig.3 Serial interface master mode format.
May 1994
1 STEREO WORD SWS FORMAT 2 idle SCK LEFT DATA n CLOCKS idle RIGHT DATA n CLOCKS SDO MSB LSB MSB LSB MSB 1 STEREO WORD
Philips Semiconductors
Bitstream conversion ADC for digital audio systems
12
SWS FORMAT 1 idle SCK
LEFT DATA n CLOCKS idle
RIGHT DATA n CLOCKS
SDO
MSB
LSB
MSB
LSB
MSB
MGA915
Preliminary specification
SAA7366
1 < n < 33. Up to 18 significant bits are available.
Fig.4 Serial interface slave mode formats.
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for digital audio systems
SAA7366
tr SCK
tf
tL
tH
timing reference levels 2.0 V 0.8 V
td SWS 2.0 V 0.8 V tr t su th tf MSB FORMAT 2 t wL 2.0 V 0.8 V
SDO
VALID
MSB FORMAT 1 t wH
SWS
MGA916
Fig.5 Serial interface master mode timing.
tr SCK td SWS 2.0 V 0.8 V tr
tf
tL
tH
timing reference levels 2.0 V 0.8 V
t su
t su
th
tf MSB FORMAT 2 t wL 2.0 V 0.8 V
SDO
VALID
MSB FORMAT 1 t wH
SWS
MGA917
Fig.6 Serial interface slave mode timing.
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Preliminary specification
Bitstream conversion ADC for digital audio systems
SAA7366
SWS t idle SCK
MGA918
t idle
Fig.7 Serial interface slave mode burst clock.
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handbook, full pagewidth
APPLICATION INFORMATION
Philips Semiconductors
Bitstream conversion ADC for digital audio systems
left channel input 100 k 47 F 47 F 47 nF
(1)
right channel input 100 k 5V 47 F
(1)
10 k R dither 270 270
10 k R dither 330 k 47 F 47 nF BOL 20
(1)
47 nF
47 F
4.7 5V 47 F VDDD or VSSD SLAVE 24 VDDA 23 VREFL 22 47 nF
(1)
620 k 10 k 68 pF BIL 21
33 k
10 k 68 pF V DACN 18 BOR 17 16 BIR VREFR 15 22 nF I REF 14 13 VSSA
VDACP 19
15
SAA7366
1 SFOR VDDD or VSSD from microcontroller power-down control to microcontroller overload detection system clock input 47 nF
(1)
2 STD
3 OVLD
4 CKIN
5 VDDD
6 VSSD
7 SDO
8 SWS
9 SCK
10 TEST1
11 HPEN
12 TEST2
VDDD or VSSD
MGA913
47 F 4.7 5V
to serial interface receiver circuit
Preliminary specification
SAA7366
(1) These capacitors should preferably be surface mounted components located as close as possible to the device pins.
Fig.8 Application circuit.
Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for digital audio systems
PACKAGE OUTLINE
SAA7366
handbook, full pagewidth
15.6 15.2
7.6 7.4
A
S 0.9 (4x) 0.4
0.1 S
10.65 10.00
24
13 2.45 2.25 1.1 1.0 0.3 0.1 0.32 0.23 2.65 2.35
pin 1 index 1 12 detail A 1.1 0.5 0 to 8o
MBC235 - 1
1.27
0.49 0.36
0.25 M (24x)
Dimensions in mm.
Fig.9 Plastic SOL, 24-pin (SO24L; SOT137A).
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Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for digital audio systems
SOLDERING Plastic small-outline packages BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7366
applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
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Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for digital audio systems
NOTES
SAA7366
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Philips Semiconductors
Preliminary specification
Bitstream conversion ADC for digital audio systems
NOTES
SAA7366
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Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil. P.O. Box 7383 (01064-970). Tel. (011)821-2327, Fax. (011)829-1849 Canada: INTEGRATED CIRCUITS: Tel. (800)234-7381, Fax. (708)296-8556 DISCRETE SEMICONDUCTORS: 601 Milner Ave, SCARBOROUGH, ONTARIO, M1B 1M8, Tel. (0416)292 5161 ext. 2336, Fax. (0416)292 4477 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (032)88 2636, Fax. (031)57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (9)0-50261, Fax. (9)0-520971 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: PHILIPS COMPONENTS UB der Philips G.m.b.H., P.O. Box 10 63 23, 20043 HAMBURG, Tel. (040)3296-0, Fax. (040)3296 213. Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 Hong Kong: PHILIPS HONG KONG Ltd., Components Div., 6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T., Tel. (852)424 5121, Fax. (852)428 6729 India: Philips INDIA Ltd, Components Dept, Shivsagar Estate, A Block , Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)640 000, Fax. (01)640 200 Italy: PHILIPS COMPONENTS S.r.l., Viale F. Testi, 327, 20162 MILANO, Tel. (02)6752.3302, Fax. (02)6752 3300. Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5028, Fax. (03)3740 0580 Korea: (Republic of) Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: Philips Components, 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB Tel. (040)783749, Fax. (040)788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546. Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)14163160/4163333, Fax. (01)14163174/4163366. Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., Components Division, 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494. Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382. Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (662)398-0141, Fax. (662)398-3319. Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 2770, Fax. (0212)269 3094 United Kingdom: Philips Semiconductors Limited, P.O. Box 65, Philips House, Torrington Place, LONDON, WC1E 7HD, Tel. (071)436 41 44, Fax. (071)323 03 42 United States: INTEGRATED CIRCUITS: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd., P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404, Tel. (800)447-3762 and (407)881-3200, Fax. (407)881-3300 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601
For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BAF-1, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD31 (c) Philips Electronics N.V. 1994
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
513061/1500/01/pp20 Document order number: Date of release: May 1994 9397 731 80011
Philips Semiconductors

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